APA

Solecki Jędrzej, Tyszer J. & Politechnika Poznańska. (2016). Testing Digital Integeated Circuits with Novel Low Power High Fault Coverage Techniques and a New Scan Architecture. Poznań: .

Chicago

Solecki Jędrzej, Tyszer Jerzy and Politechnika Poznańska. 2016. Testing Digital Integeated Circuits with Novel Low Power High Fault Coverage Techniques and a New Scan Architecture. Poznań: .

Harvard

Solecki Jędrzej, Tyszer J. and Politechnika Poznańska. (2016). Testing Digital Integeated Circuits with Novel Low Power High Fault Coverage Techniques and a New Scan Architecture. Poznań: .

MLA

Solecki Jędrzej, Tyszer Jerzy and Politechnika Poznańska. Testing Digital Integeated Circuits with Novel Low Power High Fault Coverage Techniques and a New Scan Architecture. Poznań: . 2016.